The present disclosure relates to memory management systems, and more specifically, to dynamic load-based memory tag management.
In computer and mainframe memory systems a protocol can be used across the memory channels in a memory control unit to send fetch and store commands to a memory buffer chip that interfaces to dynamic random access memory (DRAM) chips that include double data rate (DDR) memory. The protocol involves returning data and/or completion status to the memory controller for these commands. System performance can be limited under certain system work load conditions. For example, if there is a period of time where data stores dominate the traffic to memory, the amount of pre-allocated tags available to stores may be used up and limit the number of outstanding stores. This can limit store bandwidth to memory if the round-trip time for returning store completions (thus freeing up store tags) exceeds the time that it takes to transfer data from the memory controller to the memory buffer chip for the number of store tags available.